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the mark h shows major revised points. data sheet mos integrated circuit m pd75036 4 bit single-chip microcomputer the m pd75036 is a 75x series 4-bit single-chip microcomputer. the m pd75036 is an expanded version of the m pd75028. it has rom and ram with a larger capacity. the minimum instruction execution time of the m pd75036 is 0.95 m s. in addition to this high-speed capability, it contains an a/d converter and furnishes high-performance functions such as the serial bus interface (sbi) function that follows the nec standard format, providing powerful features and high cost performance. a built-in prom product, m pd75p036, is also available. the m pd75p036 is suitable for small-scale production or experimental production in system development. the following users manual describes the details of functions. be sure to read it before design. m pd75028 users manual: ieu-694 features ? variable instruction execution time advantageous to high-speed operation and power-saving: ? 0.95 m s, 1.91 m s, or 15.3 m s (at 4.19 mhz when the main system selected) ? 122 m s (at 32.768 khz when the subsystem clock selected) ? program memory (rom) capacity: 16256 8 bits ? data memory (ram) capacity: 1024 4 bits ? built-in a/d converter (8-bit resolution, successive approximation): 8 channels ? powerful timer function: 4 channels ? usable for 16-bit integral a/d conversion and pwm output ? built-in nec standard serial bus interface (sbi) ? very low-power clock operation allowed (5 m a typ. at 3 v) applications electric household appliances, air cooling/heating apparatus, cameras, and electronic measuring instruments ordering information part number package quality grade m pd75036cw- 64-pin plastic shrink dip (750 mil) standard m pd75036gc- -ab8 64-pin plastic qfp ( 14 mm) standard remark is a mask rom code number. please refer to "quality grades on nec semiconductor devices" (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. the information in this document is subject to change without notice. document no. ic-3115 (o.d. no. ic-8611) date published october 1993 p printed in japan ? nec corporation 1993
2 m pd75036 functions item function ? 0.95, 1.91, 15.3 m s (main system clock : 4.19 mhz operation) ? 122 m s (subsystem clock : 32.768 khz operation) 16256 8 bits 1024 4 bits ? 4-bit manipulation : 8 ? 8-bit manipulation : 4 ? timer/event counter ? basic interval timer : can be used as watchdog timer ? clock timer : buzzer output enabled multifunction timer : can be used as timer, free-running timer or counter for integration a/d converter, or for pwm output ? three-wire serial i/o mode ? two-wire serial i/o mode ? sbi mode 16 bits f , f x /2 3 , f x /2 4 , f x /2 6 (main system clock: 4.19 mhz operation) ? 8-bit resolution 8 channels (successive-approximation) ? capable of low-voltage operation: v dd = 2.7 to 6.0 v external : 3, internal : 4 external : 1, internal : 1 ? ceramic/crystal oscillator for main system clock oscillation ? crystal oscillator for subsystem clock oscillation stop/halt mode C40 to +85 c 2.7 to 6.0 v ? 64-pin plastic shrink dip (750 mil) ? 64-pin plastic qfp ( 14 mm) instruction execution time on-chip memory rom ram general register i/o port timer serial interface bit sequential buffer clock output a/d converter vectored interrupt test input system clock oscillator standby function operating temperature range operating voltage package ? on-chip pull-up resistor by software : 27 ? on-chip pull-down resistor by software: 4 ? direct led driving: 4 ? withstand voltage is 10 v ? on-chip pull-up resistor by mask option ? direct led driving: 4 cmos input pins cmos i/o pins n-ch open-drain i/o pins 48 12 24 12 h h 4 channels
3 m pd75036 contents 1. pin configurations (top view) ....................................................................................... 4 2. block diagram ...................................................................................................................... 6 3. pin functions ....................................................................................................................... 7 3.1 port pins ..................................................................................................................................... 7 3.2 non-port pins ........................................................................................................................... 9 3.3 pin input/output circuits .................................................................................................. 11 3.4 mask option selection ....................................................................................................... 13 3.5 connection of unused pins ................................................................................................ 14 4. architecture and memory map of the m pd75036 .................................................. 15 5. peripheral hardware functions ................................................................................ 17 5.1 ports ............................................................................................................................................. 17 5.2 clock generator .................................................................................................................... 17 5.3 clock output circuit ............................................................................................................ 19 5.4 basic interval timer .............................................................................................................. 20 5.5 clock timer ................................................................................................................................ 21 5.6 timer/event counter .............................................................................................................. 22 5.7 serial interface ...................................................................................................................... 24 5.8 a/d converter .......................................................................................................................... 26 5.9 multifunction timer (mft) .................................................................................................... 27 6. interrupt function ............................................................................................................ 29 7. standby function ................................................................................................................ 31 8. reset function ..................................................................................................................... 31 9. instruction set ................................................................................................................... 32 10. electrical characteristics .......................................................................................... 39 11. package dimensions ........................................................................................................... 52 appendix a development tools ........................................................................................ 54 appendix b related documents ........................................................................................ 55
4 m pd75036 1. pin configurations (top view) ? 64-pin plastic shrink dip ? 64-pin plastic qfp ic: internally connected (should be directly connected to v dd ) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 v ss p30 p31 p32 p33 p40 p41 p42 p43 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p80 p81 p82 p83 p90 p91 p92 p93 p10/int0 p11/int1 p12/int2 sb1/si/p03 sb0/so/p02 sck/p01 int4/p00 buz/p23 pcl/p22 ppo/p21 pto0/p20 mat/p103 maz/p102 mai/p101 mar/p100 reset x1 x2 ic xt1 xt2 v dd av dd av ref+ av ref an7 an6 an5 an4 an3/p113 an2/p112 an1/p111 an0/p110 av ss ti0/p13 pd75036cw- m 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p90 p91 p92 p93 p10/int0 p11/int1 p12/int2 ti0/p13 av ss an0/p110 an1/p111 an2/p112 an3/p113 an4 an5 an6 pto0/p20 mat/p103 maz/p102 mai/p101 mar/p100 reset x1 x2 ic xt1 xt2 v dd av dd av ref+ av ref an7 pd75036gc- -ab8 m 17 18 19 20 21 22 23 24 25 26 27 28 29 30 3132 p50 p51 p52 p53 p60/kr0 p61/kr1 p62/kr2 p63/kr3 p70/kr4 p71/kr5 p72/kr6 p73/kr7 p80 p81 p82 p83 64 63 62 6160 59 58 57 56 55 54 53 52 51 50 49 p43 p42 p41 p40 p33 p32 p31 p30 v ss sb1/si/p03 sb0/so/p02 sck/p01 int4/p00 buz/p23 pcl/p22 ppo/p21 1 2 3
5 m pd75036 mft a/d mode pin names p00-03 : port 0 : port 0 p10-13 : port 1 : port 1 p20-23 : port 2 : port 2 p30-33 : port 3 : port 3 p40-43 : port 4 : port 4 p50-53 : port 5 : port 5 p60-63 : port 6 : port 6 p70-73 : port 7 : port 7 p80-83 : port 8 : port 8 p90-93 : port 9 : port 9 p100-103: port 10 : port 10 p110-113: port 11 : port 11 kr0-7 : key return : key interrupt input sck : serial clock : serial clock i/0 si : serial input : serial data input so : serial output : serial data output sb0, 1 : serial bus 0, 1 : serial bus i/o reset : reset input : reset input ti0 : timer input 0 : external event pulse input pto0 : programmable timer output 0 : timer/event counter output buz : buzzer clock : arbitrary frequency output pcl : programmable clock : clock output int0, 1, 4: external vectored interrupt 0, 1, 4 : external vectored interrupt input int2 : external test input 2 : external test input x1, 2 : main system clock oscillation 1, 2 : main system clock oscillation pin xt1, 2 : subsystem clock oscillation 1, 2 : subsystem clock oscillation pin mar : reference integration control : reverse integration signal output mai : integration control : integration signal output maz : autozero control : autozero signal output mat : external comparate timing input : external comparator signal input ppo : programmable pulse output ... mft timer mode : pulse output ... mft timer mode an0-7 : analog input 0-7 : analog input av ref+ : analog reference (+) : analog reference voltage (+) input av ref- : analog reference (-) : analog reference voltage (-) input av dd : analog v dd : a/d converter power supply input av ss : analog v ss : a/d converter gnd input v dd : positive power supply : main power supply pin v ss : ground : gnd potential pin remark mft: multifunction timer ? ? ? ? ? ? mft a/d mode
6 m pd75036 2. block diagram basic interval timer timer/ counter 0 serial interface interrupt control watch timer a/d converter multi function timer program counter rom program memory 16256 8 bits decode and control general register ram data memory 1024 4 bits alu cy sp bank clock output control clock divider clock generator stand by control sub main cpu clock intbt intt0 intcs1 intw intmft ti0/p13 pto0/p20 si/sb1/p03 so/sb0/p02 int0/p10 sck/p01 int1/p11 int2/p12 int4/p00 kr0-kr3/p60-p63 kr4-kr7/p70-p73 buz/p23 av dd av ref+ av ref av ss an0-an3/p110-p113 an4-an7 mar/p100 mai/p101 maz/p102 mat/p103 ppo/p21 pcl/p22 xt1 xt2 x1 x2 v dd v ss reset bit sequential buffer port 0 p00-p03 port 1 p10-p13 port 2 p20-p23 port 3 p30-p33 port 4 p40-p43 port 5 p50-p53 port 6 p60-p63 port 7 p70-p73 port 8 p80-p83 port 9 p90-p93 port 10 p100-p103 port 11 p110-p113 f x /2 n f
7 m pd75036 shared pin int4 sck so/sb0 si/sb1 int0 int1 int2 ti0 pto0 ppo pcl buz C C C C C C 3. pin functions 3.1 port pins (1/2) pin p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 note 2 p31 note 2 p32 note 2 p33 note 2 p40 - p43 note 2 p50 - p53 note 2 i/o circuit type note 1 f -a f -b f -c f -c e-b e-b m m input/ output input i/o i/o i/o input i/o i/o i/o i/o when reset input input input input high level (when pull- up resistors are provided) or high impedance high level (when pull- up resistors are provided) or high impedance 8-bit i/o function 4-bit input port (port0). for p01 - p03, pull-up resistors can be provided by software in units of 3 bits. with noise elimination function 4-bit input port (port1). pull-up resistors can be provided by software in units of 4 bits. 4-bit i/o port (port2). pull-up resistors can be provided by software in units of 4 bits. programmable 4-bit i/o port (port3). i/o can be specified bit by bit. pull-up resistors can be provided by software in units of 4 bits. n-ch open-drain 4-bit i/o port (port4). a pull-up resistor can be provided for each bit (mask option). this open- drain port has a withstand voltage of 10 v. n-ch open-drain 4-bit i/o port (port5). a pull-up resistor can be provided for each bit (mask option). this open-drain port has a withstand voltage of 10 v. notes 1. the circle ( ) indicates the schmitt trigger input. 2. can directly drive the led. b b f m f
8 m pd75036 3.1 port pins (2/2) i/o circuit type note 1 f -a f -a e-b e-d m y-a input/ output shared pin when reset 8-bit i/o function p60 p61 p62 p63 p70 p71 p72 p73 p80-p83 p90-p93 p100 note 2 p101 note 2 p102 note 2 p103 note 2 p110 p111 p112 p113 pin i/o i/o i/o i/o i/o input kr0 kr1 kr2 kr3 kr4 kr5 kr6 kr7 C C mar mai maz mat an0 an1 an2 an3 programmable 4-bit i/o port (port6). i/o can be specified bit by bit. pull-up resistors can be provided by software in units of 4 bits. 4-bit i/o port (port7). pull-up resistors can be provided by software in units of 4 bits. 4-bit i/o port (port8). pull-up resistors can be provided by software in units of 4 bits. 4-bit i/o port (port9). pull-down resistors can be provided by software in units of 4 bits. n-ch open-drain 4-bit i/o port (port10). a pull-up resistor can be provided bit by bit (mask option). this open-drain port has a withstand voltage of 10 v. 4-bit input port (port11) input input input input high level (when pull-up resistors are provided) or high imped- ance input notes 1. the circle ( ) indicates the schmitt trigger input. 2. can directly drive the led. f f
9 m pd75036 3.2 non-port pins (1/2) pin ti0 pto0 pcl buz sck so/sb0 si/sb1 int4 int0 int1 int2 kr0 - kr3 kr4-kr7 mar mai maz mat ppo an0 - an3 an4 - an7 av ref+ av ref- av dd av ss i/o circuit type note 1 f -c e-b e-b e-b f -a f -b f -c f -c f -c f -a f -a m m m m e-b y-a y z-a z-a C C shared pin p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p60 - p63 p70 - p73 p100 p101 p102 p103 p21 p110 - p113 C C C C C when reset C input input input input input input C C C input input note 4 note 4 note 4 note 4 input input C C C C input/ output input i/o i/o i/o i/o i/o i/o input input input i/o i/o i/o i/o i/o i/o i/o input input input C C function input for receiving external event pulse signal for timer/event counter timer/event counter output clock output output for arbitrary frequency output (for buzzer output or system clock trimming) serial clock i/o serial data output serial bus i/o serial data input serial bus i/o edge detection vectored interrupt input (either rising edge or falling edge detection) edge detection vectored interrupt input (detection edge selectable) edge detection testable input (rising edge detection) parallel falling edge detection testable input parallel falling edge detection testable input in mft integral a/d converter mode in mft timer mode for a /d converter only note 2 note 3 note 3 reverse integration signal output integration signal output autozero signal output comparator input timer pulse output 8-bit analog input reference voltage input (on av dd side) reference voltage input (on av ss side) operating power supply reference gnd potential notes 1. the circle ( ) indicates the schmitt trigger input. 2. clock synchronous 3. asynchronous 4. high level (when pull-up resistors are provided) or high impedance remark mft: multifunction timer b f f m b b b f f
10 m pd75036 3.2 non-port pins (2/2) pin x1, x2 xt1, xt2 reset ic v dd v ss i/o circuit type note C C C C C shared pin C C C C C C when reset C C C C C C input/ output function crystal/ceramic connection for main system clock generation. when external clock signal is used, it is applied to x1, and its reverse phase signal is applied to x2. crystal connection for subsystem clock genera- tion. when external clock signal is used, it is applied to xt1, and its reverse phase signal is applied to xt2, xt1 can be used as a 1-bit input (test). system reset input internally connected. (to be directly connected to v dd ) positive power supply gnd potential input input input C C C note the circle ( ) indicates the schmitt trigger input. b
11 m pd75036 3.3 pin input/output circuits the input/output circuit of each m pd75036 pin is shown below in a simplified manner. type a (for type e-b) cmos input buffer schmitt trigger input with hysteresis push-pull output which can be set to high-impedance output (off for both p-ch and n-ch) p.u.r.: pull-up resistor p.u.r.: pull-up resistor type b type e-b type b-c type d (for type e-b, f-a) v dd in p-ch n-ch in in p-ch p.u.r. enable p.u.r. v dd v dd p-ch n-ch out data output disable p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type a (1/3) n-ch p.d.r. p.d.r. enable p.d.r.: pull-down resistor type a type d data output disable in/out type e-d
12 m pd75036 type f-b type f-a type m type y type m-c type y-a p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r.: pull-up resistor p.u.r. v dd p.u.r. enable p-ch in/out data output disable type d type b v dd p-ch n-ch in/out v dd p-ch p.u.r. p.u.r. enable output disable (p) data output disable output disable (n) n-ch (can sustain +10 v) in/out data v dd output disable p.u.r. enable (mask option) middle-voltage input buffer (can sustain +10 v) n-ch p.u.r. data output disable p.u.r. enable v dd p-ch in/out av dd av dd p-ch av ss n-ch sampl- ing c av ss reference voltage (from voltage tap of serial resistor string) input enable in av dd av ss sampl- ing c av dd av ss in p-ch n-ch reference voltage (from voltage tap of serial resistor string) input buffer in + + (2/3)
13 m pd75036 pin name p40 - p43, p50 - p53, p100-p103 xt1, xt2 1 pull-up resistor provided (specifiable bit by bit) 1 feedback resistor provided (if a subsystem clock is used) 2 pull-up resistor not provided (specifiable bit by bit) 2 feedback resistor not provided (if a subsystem clock is not used) mask option 3.4 mask option selection the following mask options are available for selection for each pin. type z-a av ref+ av ref- reference voltage (3/3)
14 m pd75036 3.5 connection of unused pins pin recommended connection p00/int4 p01/sck p02/so/sb0 p03/si/sb1 p10/int0-p12/int2 p13/ti0 p20/pto0 p21/ppo p22/pcl p23/buz p30-p33 p40-p43 p50-p53 p60/kr0-p63/kr3 p70/kr4-p73/kr7 p80-p83 p90-p93 p100/mar p101/mai p102/maz p103/mat p110/an0-p113/an3 an4-an7 av ref+ av ref- av ss av dd xt1 xt2 ic to be connected to v ss to be connected to v ss or v dd to be connected to v ss input state : to be connected to v ss or v dd output state:to be open to be connected to v ss or v dd to be connected to v ss to be connected to v dd to be connected to v ss or v dd to be open to be directly connected to v dd h
15 m pd75036 4. architecture and memory map of the m pd75036 the m pd75036 has two architectural features: ? bank configuration of data memory : static ram (1024 words 4 bits) peripheral hardware (128 4 bits) ? memory mapped i/o fig. 4-1 and 4-2 show the memory maps for the m pd75036. fig. 4-1 program memory map remark in addition to the above, the br pcde and br pcxa instructions can cause a branch to an address with only the low-order 8 bits of the pc changed. mbe 0 76 0000h mbe 0 0002h mbe 0 0004h mbe 0 0006h mbe 0 0008h mbe 0 000ah 0020h 007fh 0080h 1fffh 0 internal reset start address (high-order 6 bits) internal reset start address (low-order 8 bits) intbt/int4 start address (high-order 6 bits) intbt/int4 start address (low-order 8 bits) int0 start address (high-order 6 bits) int0 start address (low-order 8 bits) int1 start address (high-order 6 bits) int1 start address (low-order 8 bits) intcsi start address (high-order 6 bits) intcsi start address (low-order 8 bits) intt0 start address (high-order 6 bits) intt0 start address (low-order 8 bits) intmft start address (high-order 6 bits) intmft start address (low-order 8 bits) geti instruction reference table call !addr instruction subroutine entry address br !addr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) callf !faddr instruc- tion entry address brcb !caddr instruc- tion branch address mbe 0 000ch 1000h 0fffh 0800h 07ffh 2000h 2fffh branch address and subroutine entry address specified in geti instruction address 0 0 0 0 0 0 0 5 3f7fh brcb !caddr instruc- tion branch address brcb !caddr instruc- tion branch address brcb !caddr instruc- tion branch address 3000h
16 m pd75036 fig. 4-2 data memory map (8 4) data memory 000h 007h 008h 2ffh 300h 3ffh f80h fffh 256 4 256 4 128 4 0 2 15 stack area general register area data area static ram (1024 4) peripheral hardware area not contained 256 4 256 4 1 3 0ffh 100h 1ffh 200h memory bank
17 m pd75036 5. peripheral hardware functions 5.1 ports the m pd75036 has the following three types of i/o port: ? 12 cmos input ports (ports 0, 1, and 11) ? 24 cmos i/o ports (ports 2, 3, 6, 7, 8, and 9) ? 12 n-ch open-drain i/o ports (ports 4, 5, and 10) total: 48 ports table 5-1 functions of ports remarks port (symbol) port0 port1 port3 note port6 port2 port7 port4 note port5 note port10 note port8 port9 port11 allows input and test at any time regardless of the operation modes of dual function pins. allows input or output mode setting in units of one bit. allows input or output mode setting in units of four bits. ports 6 and 7 make a pair, allowing data i/o in units of eight bits. allows input or output mode setting in units of four bits. ports 4 and 5 make a pair, allowing data i/o in units of eight bits. allows input or output mode setting in units of four bits. port for 4-bit input also used as so/sb0, si/ sb1, sck, int0-int2, int4, and ti0 pins. port 6 is also used as kr0- kr3 pins. port 2 is also used as pto0, ppo, pcl, and buz pins. also used as kr4-kr7 pins. use of an internal pull-up registor can be mask- programmed in units of one bit. port 10 is also used as mar, mai, maz, and mat pins. port 11 is also used as an0- an3 pins. 4-bit input 4-bit i/o 4-bit i/o (n-ch open-drain, withstand voltage: 10 v) 4-bit i/o 4-bit input operation and feature function note ports 3, 4, 5 and 10 can directly drive an led. 5.2 clock generator operation of the clock generator is specified by the processor clock control register (pcc) and system clock control register (scc). the main system clock or subsystem clock can be selected. the instruction execution time is variable. ? 0.95 m s, 1.91 m s, 15.3 m s (main system clock: 4.19 mhz) ? 122 m s (subsystem clock: 32.768 khz)
18 m pd75036 fig. 5-1 block diagram of the clock generator note instruction execution remarks 1. f x : main system clock frequency 2. f xt : subsystem clock frequency 3. f = cpu clock 4. pcc: processor clock control register 5. scc: system clock control register 6. one clock cycle (t cy ) of the cpu clock ( f ) is equal to one machine cycle of an instruction. see chapter 10 for details of t cy . h subsystem clock generator main system clock generator clock timer multifunction timers basic interval timer (bt) timer/event counter serial interface clock timer a/d converter (successive approximation) int0 noise eliminator clock output circuit ? ? ? ? ? ? ? ? ? ? 1/2 to 1/4096 frequency divider selec- tor selec- tor frequency divider f oscillator disable signal internal bus halt note stop note pcc2, pcc3 clear signal wait release signal from bt standby release signal from interrupt control circuit reset signal xt1 xt2 x1 x2 4 scc scc3 scc0 pcc pcc0 pcc1 pcc2 pcc3 stop f/f qs r halt f/f s q r f xt f x 1/2 1/16 1/4 wm.3 cpu int0 noise eliminator clock output circuit ? ? v dd v dd
19 m pd75036 5.3 clock output circuit the clock output circuit outputs a clock pulse signal on the p22/pcl pin for remote control or for supplying clock pulses to a peripheral lsi device. fig. 5-2 configuration of the clock output circuit remark the clock output circuit is designed so that pulses with short widths do not appear in enabling or disabling clock output. from the clock generator clom selector output buffer port 2 input/ output mode specification bit p22 output latch pcl/p22 internal bus 4 f f x /2 3 f x /2 4 f x /2 6 port2.2 bit 2 of pmgb clom0 clom1 clom2 clom3
20 m pd75036 5.4 basic interval timer the basic interval timer provides the following functions: ? interval timer operation that generates a reference time interrupt ? application of watchdog timer for detecting program crashes ? selection of a wait time for releasing the standby mode, and counting ? reading the count value fig. 5-3 configuration of the basic interval timer note instruction execution from the clock generator internal bus 4 f x /2 5 f x /2 7 f x /2 9 f x /2 12 mpx basic interval timer (8-bit frequency divider circuit) clear signal clear signal bt interrupt request flag vectored interrupt request signal irqbt wait release signal for standby release set signal bt 8 btm3 btm2 btm1 btm0 btm set1 note 3
21 m pd75036 5.5 clock timer the m pd75036 contains one channel for a clock timer. the clock timer provides the following functions: ? the clock timer sets the test flag (irqw) every 0.5 seconds. the standby mode can be released with irqw. ? either the main system clock or subsystem clock can produce 0.5-second intervals. ? the fast-forward mode produces an interval 128 times faster (3.91 ms), which is useful for program debugging and testing. ? an arbitrary frequency (2.048, 4.096, or 32.768 khz) can be output to the p23/buz pin, so that it can be used for sounding the buzzer and system clock frequency trimming. ? the frequency divider can be cleared, so the clock can start from zero seconds. fig. 5-4 block diagram of the clock timer the values in parentheses indicates are for f x = 4.194304 mhz and f xt = 32.768 khz p23/buz internal bus 8 selector from the clock gener- ator f x 128 (32.768 khz) f xt (32.768 khz) ? ? ? ? ? selector frequency divider selector intw irqw set signal 2 hz 0.5 sec wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 p23 output latch bit 2 of pmgb port2.3 output buffer clear signal f w (32.768 khz) bit test instruction port 2 input/ output mode wm 4 khz 2 khz f w 2 7 (256 hz: 3.91 ms) f w 2 14
22 m pd75036 5.6 timer/event counter the m pd75036 contains one channel of timer/event counter. the timer/event counter provides the following functions: ? programmable interval timer operation ? output of a square wave at a given frequency to the pto0 pin ? event counter operation ? frequency divider operation that divides ti0 pin input by n and outputs the result to the pto0 pin ? supply of serial shift clock signal to a serial interface circuit ? function of reading the state of counting
23 m pd75036 fig. 5-5 block diagram of the timer/event counter note instruction execution count register (8) p13/ ti0 mpx timer operation start signal ? ? ? ? 8 8 8 from the clock generator internal bus tm06 tm05 tm04 tm03 tm02 port1.3 (see fig. 5-1 .) comparator (8) modulo register (8) to enable flag p20 output latch signal port 2 input/ output mode clear signal t0 tmod0 bit 2 of pgmb p20/pto0 output buffer reset reset irqt0 clear signal tout f/f tm0 set1 note input buffer irqt0 set signal intt0 port2.0 toe0 to serial interface cp match 8 8 tm01 tm00 tm07
24 m pd75036 5.7 serial interface the m pd75036 has three modes. ? three-wire serial i/o mode (the first bit is switchable between msb and lsb.) ? two-wire serial i/o mode (the first bit is msb.) ? sbi mode (the first bit is msb.) the three-wire serial i/o mode enables connections to be made with the 75x series, 78k series, and many other types of i/o devices. the two-wire serial i/o mode and sbi mode enable communication with two or more devices.
25 m pd75036 fig. 5-6 block diagram of the serial interface internal bus 8 8 8 8/4 p03/si/sb1 p02/so/sb0 p01/sck (8) f x /2 3 f x /2 4 f x /2 6 tout f/f (from timer/event counter) csim reld cmdd ackd ackt acke bsye relt cmdt dq set clr (8) (8) sbic bit test slave address register (sva) address comparator shift register (sio) match signal bit manipulation so latch bit test selec- tor selec- tor busy/ acknowledge output circuit bus release/ command/ acknowledge detection circuit serial clock counter serial clock control circuit intcsi control circuit irqcsi set signal intcsi p01 output latch serial clock selector external sck
26 m pd75036 5.8 a/d converter the m pd75036 contains an 8-bit resolution analog/digital (a/d) converter that has eight analog input channels (an0 - an7). the a /d converter employs the successive-approximation method. fig. 5-7 configuration of the a/d converter internal bus 8 + an0/p110 an1/p111 an2/p112 an3/p113 an4 an5 an6 an7 av ref+ av ref-- r 8 r r/2 r/2 8 adm 0 0 eoc soc adm4 adm5 adm6 0 control circuit multi- plexer sample and hold circuit comparator sa register (8) tap decoder series resistor string r
27 m pd75036 5.9 multifunction timer (mft) the m pd75036 contains one multifunction timer (mft). the mft has four operation modes. each mode provides the following functions: ? 8-bit timer mode ? operates as a programmable interval timer. ? outputs a square wave of an arbitrary frequency on the ppo pin. ? pwm output mode ? outputs a 6-bit, 7-bit, or 8-bit precision pwm signal on the ppo pin. ? 16-bit free-running timer mode ? operates as an interval timer that generates an interrupt at specified time intervals. ? usable as a one-shot timer. ? integral a/d converter modes ? outputs a control signal for a 16-bit integral a/d converter. ? allows a resolution to be selected from 13 bits, 14 bits, 15 bits, and 16 bits.
28 m pd75036 fig. 5-8 block diagram of the multifunction timer selector selector selector clear signal count register (mftl) modulo latch comparator count register (mfth) mat/ p103 edge selector mpx f x /2 f x /2 3 f x /2 5 f x /2 7 f x /2 9 f x /2 11 mftm7 mftm6 mftm5 mftm4 mftm3 mftm2 mftm1 mftm0 mftc3 mftc2 mftc1 mftc0 mftc mftm tap selector interrupt selector 1/4 8 overflow match integral a/d control circuit output latch p21 p100 p101 p102 input/output mode register maz/p102 mai/p101 mar/p100 ppo/p21 intmft irqmft set signal irqmft clear signal reset internal bus internal bus 8 8 mft f/f 8 8
29 m pd75036 6. interrupt function the m pd75036 has nine vectored interrupt sources and provides multiple interrupts by software control. it also has two types of edge detected testable input pins. the interrupt control circuitry of the m pd75036 has the following features: ? vectored interrupts are controlled by the hardware. whether to accept an interrupt is controlled by an interrupt flag (ie ) and interrupt master enable flag (ime). ? an interrupt start address can be freely set. ? an interrupt request flag (irq ) can be tested. (whether an interrupt has occurred can be checked by software.) ? a standby mode can be released. (what interrupt source to release can be selected using an interrupt enable flag.)
30 m pd75036 fig. 6-1 block diagram of interrupt control circuit 2 im2 22 irqbt irq4 irq0 irq1 irqcsi irqt0 irqmft irqw irq2 int bt int4/ p00 int0/ p10 int1/ p11 intcsi intt0 intmft intw int2/ p12 both-edge detection circuit im1 im0 edge detection circuit edge detection circuit rising edge detection circuit falling edge detection circuit kr0/p60 kr7/p73 selec- tor im2 interrupt enable flag (ie ) ist0 ime priority control circuit decoder vrqn vector table address generator standby release signal internal bus note note noise eliminator
31 m pd75036 halt instruction this mode can be set when either the main system clock or s ubsystem clock is used. only cpu clock f is stopped (with oscilla- tion continued). operation is possible only when the main system clock is oscillated. (sets irqbt at reference time intervals) operation is possible only when external sck input is selected for the serial clock or the main system clock is oscillated. operation is possible only when ti0 pin input is selected for the count count clock or the main system clock is oscillated. operation is possible. operation is possible. note operation is possible. note interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or reset input stop instruction this mode can be set only when the main system clock is used. only the main system clock is stopped. operation is stopped. operation is p ossible only when external sck input is selected for the serial clock. operation is possible only when ti0 pin input is selected for the count clock. operation is possible when f xt is selected for the count clock. operation is stopped. operation is stopped. interrupt request signals sent out from hardware, which are enabled by interrupt enable flags, or reset input note operation is possible only when the main system clock operates. 8. reset function the m pd75036 is reset by reset signal input. 7. standby function to reduce the power consumption of the system waiting for a program input, the m pd75036 has two standby modes stop and halt modes. table 7-1 standby modes and operation status stop mode halt mode instruction for setting system clock at setting clock generator basic interval timer serial interface timer/event counter clock timer a/d converter multifunction timer external interrupt cpu release signal int1, int2, and int4 are enabled. int0 is disabled. operation is stopped. operation status
32 m pd75036 9. instruction set (1) operand identifier and its descriptive method the operands are described in the operand column of each instruction according to the descriptive method for the operand format of the appropriate instructions (refer to ra75x assembler package user's manual, language (eeu-1363) for details). for descriptions in which alternatives exist, one element should be selected. capital letters and plus and minus signs are keywords; therefore, they should be described as they are. for immediate data, the appropriate numerical values or labels should be described. note only even address can be specified for mem when processing 8-bit data. (2) symbol definitions in operation description a : a register; 4-bit accumulator b : b register c : c register d : d register e : e register h : h register l : l register identifier reg reg1 rp rp1 rp2 rpa rpa1 n4 n8 mem note bit fmem pmem addr caddr faddr taddr portn ie mbn description x, a, b, c, d, e, h, l x, b, c, d, e, h, l xa, bc, de, hl bc, de, hl bc, de hl, de, dl de, dl 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label 2-bit immediate data or label fb0h - fbfh, ff0h - fffh immediate data or label fc0h - fffh immediate data or label 0000h - 3f7fh immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20h - 7fh immediate data (however, bit 0 = 0) or label port0 - port11 iebt, iecsi, iet0, ie0, ie1, ie2, ie4, iew, iemft mb0, mb1, mb2, mb3, mb15
33 m pd75036 x : x register xa : pair register (xa); 8-bit accumulator bc : pair register (bc) de : pair register (de) hl : pair register (hl) pc : program counter sp : stack pointer cy : carry flag; bit accumulator psw : program status word mbe : memory bank enable flag portn : port n (n = 0 to 11) ime : interrupt master enable flag ie : interrupt enable flag mbs : memory bank selection register pcc : processor clock control register . : address bit delimiter ( ) : contents addressed by h : hexadecimal data (3) explanation of the symbols in the addressing area field remarks 1. mb indicates an accessible memory bank. 2. for *2, mb is always 0 irrespective of mbe and mbs. 3. for *4 and *5, mb is always 15 irrespective of mbe and mbs. 4. *6 to *10 indicate each addressable area. mb = mbe?mbs (mbs = 0, 1, 2, 3, or 15) mb = 0 mbe = 0: mb = 0 (00h-7fh) mb = 15 (80h-ffh) mbe = 1: mb = mbs (mbs = 0, 1, 2, 3, or 15) mb = 15, fmem = fb0h-fbfh or ff0h-fffh mb = 15, pmem = fc0h-fffh addr = 0000h-3f7fh addr = (current pc) - 15 to (current pc) - 1 or (current pc) + 2 to (current pc) + 16 caddr = 0000h-0fffh (pc 13,12 = 00b) or 1000h-1fffh (pc 13,12 = 01b) or 2000h-2fffh (pc 13,12 = 10b) or 3000h-3f7fh (pc 13,12 = 11b) faddr = 0000h-07ffh taddr = 0020h-007fh *1 *2 *3 *4 *5 *6 *7 *8 *9 *10 data memory addressing program memory addressing
34 m pd75036 (4) description of machine cycle column s indicates the number of machine cycles necessary for skipping any skip instruction. the value of s changes as follows: ? when no skip is performed s = 0 ? when a 1-byte or 2-byte instruction is skipped s = 1 ? when a 3-byte instruction (br !addr, call !addr instruction) is skipped s = 2 caution the geti instruction is skipped in one machine cycle. one machine cycle is equivalent to one cpu clock f cycle (t cy ). therefore, the length of the machine cycle can be selected from three different lengths by the pcc setting.
35 m pd75036 group transfer table reference arithme- tic mne- monic mov xch movt adds addc subs subc and or xor operand a, #n4 reg1, #n4 xa, #n8 hl, #n8 rp2, #n8 a, @hl a, @rpa1 xa, @hl @hl, a @hl, xa a, mem xa, mem mem, a mem, xa a, reg1 xa, rp reg1, a rp1, xa a, @hl a, @rpa1 xa, @hl a, mem xa, mem a, reg1 xa, rp xa, @pcde xa, @pcxa a, #n4 a, @hl a, @hl a, @hl a, @hl a, #n4 a, @hl a, #n4 a, @hl a, #n4 a, @hl bytes 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 1 1 1 1 1 1 1 2 1 2 1 2 1 machin- ing cycle 1 2 2 2 2 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 2 2 2 1 2 3 3 1 + s 1 + s 1 1 + s 1 2 1 2 1 2 1 skip condition string a string a string b carry carry borrow address- ing area *1 *2 *1 *1 *1 *3 *3 *3 *3 *1 *2 *1 *3 *3 *1 *1 *1 *1 *1 *1 *1 operation a n4 reg1 n4 xa n8 hl n8 rp2 n8 a (hl) a (rpa1) xa (hl) (hl) a (hl) xa a (mem) xa (mem) (mem) a (mem) xa a reg1 xa rp reg1 a rp1 xa a (hl) a (rpa1) xa (hl) a (mem) xa (mem) a reg1 xa rp xa (pc 13-8 + de) rom xa (pc 13-8 + xa) rom a a + n4 a a + (hl) a, cy a + (hl) + cy a a C (hl) a, cy a C (hl) C cy a a ? n4 a a ? (hl) a a M n4 a a M (hl) a a M n4 a a M (hl)
36 m pd75036 group accumulator manipulation increment/ decrement compari- son carry flag manipu- lation memory bit manipula- tion mne- monic rorc not incs decs ske set1 clr1 skt not1 set1 clr1 skt skf sktclr and1 or1 operand a a reg @hl mem reg reg, #n4 @hl, #n4 a, @hl a, reg cy cy cy cy mem.bit fmem.bit pmem.@l @h+mem.bit mem.bit fmem.bit pmem.@l @h+mem.bit mem.bit fmem.bit pmem.@l @h+mem.bit mem.bit fmem.bit pmem.@l @h+mem.bit fmem.bit pmem.@l @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h+mem.bit cy, fmem.bit cy, pmem.@l cy, @h+mem.bit bytes 1 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 machin- ing cycle 1 2 1 + s 2 + s 2 + s 1 + s 2 + s 2 + s 1 + s 2 + s 1 1 1 + s 1 2 2 2 2 2 2 2 2 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 + s 2 2 2 2 2 2 skip condition reg = 0 (hl) = 0 (mem) = 0 reg = fh reg = n4 (hl) = n4 a = (hl) a = reg cy = 1 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@l) = 0 (@h + mem.bit) = 0 (fmem.bit) = 1 (pmem.@l) = 1 (@h + mem.bit) = 1 address- ing area *1 *3 *1 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 operation cy a 0 , a 3 cy, a nC1 a n a a reg reg + 1 (hl) (hl) + 1 (mem) (mem) + 1 reg reg C 1 skip if reg = n4 skip if (hl) = n4 skip if a = (hl) skip if a = reg cy 1 cy 0 skip if cy = 1 cy cy (mem.bit) 1 (fmem.bit) 1 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 1 (h + mem 3-0 .bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem 7-2 + l 3-2 .bit(l 1-0 )) 0 (h + mem 3-0 .bit) 0 skip if (mem.bit) = 1 skip if (fmem.bit) = 1 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 skip if (h + mem 3-0 .bit) = 1 skip if (mem.bit) = 0 skip if (fmem.bit) = 0 skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 0 skip if (h + mem 3-0 .bit) = 0 skip if (fmem.bit) = 1 and clear skip if (pmem 7-2 + l 3-2 .bit(l 1-0 )) = 1 and clear skip if (h + mem 3-0 .bit) = 1 and clear cy cy ? (fmem.bit) cy cy ? (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy cy ? (h + mem 3-0 .bit) cy cy M (fmem.bit) cy cy M (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy cy M (h + mem 3-0 .bit)
37 m pd75036 group memory bit manipula- tion branch subrou- tine stack control interrupt control input/ output cpu control mne- monic xor1 br brcb call callf ret rets reti push pop ei di in note out note halt stop nop operand cy, fmem.bit cy, pmem.@l cy, @h+mem.bit addr !addr $addr !caddr !addr !faddr rp bs rp bs ie ie a, portn xa, portn portn, a portn, xa bytes 2 2 2 C 3 1 2 3 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 machin- ing cycle 2 2 2 C 3 2 2 3 2 3 3 + s 3 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 skip condition uncondi- tional address- ing area *4 *5 *1 *6 *6 *7 *8 *6 *9 operation cy cy M (fmem.bit) cy cy M (pmem 7-2 + l 3-2 .bit(l 1-0 )) cy cy M (h + mem 3-0 .bit) pc 13-0 addr (appropriate instructions are selected from br !addr, brcb !caddr, and br $addr by the assembler.) pc 13-0 addr pc 13-0 addr pc 13-0 pc 13, 12 + caddr 11-0 (sp C 4)(sp C 1)(sp C 2) pc 11-0 (sp C 3) mbe, 0, pc 13 , pc 12 pc 13-0 addr, sp sp C 4 (sp C 4)(sp C 1)(sp C 2) pc 11-0 (spC3) mbe, 0, pc 13 , pc 12 pc 13-0 000, faddr, sp sp C 4 mbe, 0, pc 13 , pc 12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) sp sp + 4 mbe, 0, pc 13 , pc 12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) sp sp + 4, then skip unconditionally mbe, 0, pc 13 , pc 12 (sp + 1) pc 11-0 (sp)(sp + 3)(sp + 2) psw (sp + 4)(sp + 5), sp sp + 6 (sp C 1)(sp C 2) rp, sp sp C 2 (sp C 1) mbs, (sp C 2) 0, sp sp C 2 rp (sp + 1)(sp), sp sp + 2 mbs (sp + 1), sp sp + 2 ime 1 ie 1 ime 0 iexxx 0 a portn (n = 0 - 11) xa portn +1 ,portn (n = 4, 6) portn a (n = 2 - 10) portn +1 ,portn xa (n = 4, 6) set halt mode (pcc.2 1) set stop mode (pcc.3 1) no operation
38 m pd75036 caution when executing the in/out instruction, mbe must be set to 0 or mbe and mbs must be set to 1 and 15, respectively. group special mne- monic sel geti operand mbn taddr bytes 2 1 machin- ing cycle 2 3 skip condition depends on the reference instruction address- ing area *10 operation mbs n (n = 0, 1, 2, 3, or 15) ? for the tbr instruction pc 13-0 (taddr) 5-0 + (taddr + 1) ? for the tcall instruction (sp C 4)(sp C 1)(sp C 2) pc 11-0 (sp C 3) mbe, 0, pc 13 , pc 12 pc 13-0 (taddr) 5-0 + (taddr + 1) sp sp C 4 ? for other than the tbr and tcall instruction (taddr) (taddr + 1) is executed. ----------------- ----------------- ---------------------------------------------- ----------------------------------------------
39 m pd75036 10. electrical characteristics absolute maximum ratings (t a = 25 c) note calculate rms with [rms] = [peak value] duty. parameter supply voltage input voltage output voltage high-level output current low-level output current operating tem- perature storage tempera- ture unit v v v v v ma ma ma ma ma ma ma ma ma ma ?c ?c symbol v dd v i1 v i2 v o i oh i ol note t opt t stg built-in pull-up resistor open drain ports 4, 5, and 10 peak value rms peak value rms peak value rms peak value rms conditions ports other than ports 4, 5, and 10 1 pin all pins 1 pin of parts 0, 3, 4, and 5 1 pin of ports other than ports 0, 3, 4 and 5 total of all pins of ports 3 to 9 and 11 total of all pins of ports 0, 2, and 10 rated value C0.3 to +7.0 C0.3 to v dd + 0.3 C0.3 to v dd + 0.3 C0.3 to +11 C0.3 to v dd + 0.3 C10 C30 30 15 20 5 170 120 30 20 C40 to +85 C65 to +150 h
40 m pd75036 characteristics of the main system clock oscillator (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) notes 1. the oscillator frequency and input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. the oscillation settling time means the time required for the oscillation to settle after v dd is applied or after the stop mode is released. 3. when 4.19 mhz < f x 5.0 mhz, do not select pcc = 0011 as the instruction execution time. when pcc = 0011, one machine cycle falls short of 0.95 m s, the minimum value for the standard. caution when the main system clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v dd . it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. recommended constant ceramic resonator crystal resonator external clock oscillator frequency (f x ) note 1 oscillation settling time note 2 oscillator frequency (f x ) note 1 oscillation settling time note 2 x1 input frequency (f x ) note 1 x1 input high/low level width (t xh , t xl ) resonator parameter mhz ms mhz ms ms mhz ns 4.19 min. typ. max. unit conditions 5.0 4 5.0 note 3 10 30 5.0 500 1.0 1.0 1.0 100 v dd = 4.5 to 6.0 v x1 x2 v dd v dd c2 c1 x1 x2 v dd v dd c2 c1 x1 x2 m pd74hcu04
41 m pd75036 characteristics of the subsystem clock oscillator (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) notes 1. the oscillator frequency and input frequency indicate only the oscillator characteristics. see the item of ac characteristics for the instruction execution time. 2. the oscillation settling time means the time required for the oscillation to settle after v dd reaches min. of the oscillation voltage range. caution when the subsystem clock oscillator is used, conform to the following guidelines when wiring at the portions of surrounded by dotted lines in the figures above to eliminate the influence of the wiring capacity. ? the wiring must be as short as possible. ? other signal lines must not run in these areas. ? any line carrying a high fluctuating current must be kept away as far as possible. ? the grounding point of the capacitor of the oscillator must have the same potential as that of v dd . it must not be grounded to ground patterns carrying a large current. ? no signal must be taken from the oscillator. when the subsystem clock is used, pay special attention to its wiring; the subsystem clock oscillator has low amplification to minimize current consumption and is more likely to malfunc- tion due to noise than the main system clock oscillator. capacitance (t a = 25 c, v dd = 0 v) recommended constant oscillator frequency (f xt ) note 1 oscillation settling time note 2 xt1 input frequency (f xt ) note 1 xt1 input high/low level width (t xth , t xtl ) crystal resonator external clock resonator parameter khz s s khz m s 32.768 1.0 32 32 5 35 2 10 100 15 min. typ. max. unit conditions v dd = 4.5 to 6.0 v input capacitance output capacitance i/o capacitance c i c o c io symbol parameter 15 15 15 pf pf pf unit max. typ. min. f = 1 mhz 0 v for pins other than pins to be measured conditions xt1 xt2 v dd v dd r c4 c3 xt1 xt2
42 m pd75036 parameter high-level input voltage low-level input voltage high-level output voltage low-level output voltage high-level input leakage current low-level input leakage current high-level output leakage current low-level output leakage current built-in pull-up resistor built-in pull-down resistor dc characteristics (t a = -40 to +85 c, v dd = 2.7 to 6.0 v) ports 2, 3, 8, 9, and 11 ports 0, 1, 6, and 7 and reset x1, x2, xt1, and xt2 ports 2 to 5 and 8 to 11 ports 0, 1, 6, and 7 and reset x1, x2, xt1, and xt2 v dd = 4.5 to 6.0 v, i oh = C1 ma i oh = C100 m a conditions ports 3, 4, and 5 v dd = 4.5 to 6.0 v, i ol = 1.6 ma i ol = 400 m a sb0 and sb1 v i = v dd v i = 10 v v i = 0 v v o = v dd v o = 10 v v o = 0 v ports 4, 5, and 10 min. 0.7v dd 0.8v dd 0.7v dd 0.7v dd v dd C 0.5 0 0 0 v dd C 1.0 v dd C 0.5 15 30 15 10 10 10 typ. 0.5 40 40 40 max. v dd v dd v dd 10 v dd 0.3v dd 0.2v dd 0.4 2.0 0.4 0.5 0.2v dd 3 20 20 C3 C20 3 20 C3 80 300 70 60 70 60 unit v v v v v v v v v v v v v v m a m a m a m a m a m a m a m a k w k w k w k w k w k w open drain pull-up resistor: 1 k w or more other than x1, x2, xt1, and xt2 x1, x2, xt1, and xt2 ports 4, 5, and 10 (open drain) other than x1, x2, xt1, and xt2 x1, x2, xt1, and xt2 other than ports 4, 5, and 10 ports 4, 5, and 10 (open drain) built-in pull-up resistor open drain v dd = 4.5 to 6.0 v, i ol = 15 ma symbol v ih1 v ih2 v ih3 v ih4 v il1 v il2 v il3 v oh v ol i lih1 i lih2 i lih3 i lil1 i lil2 i loh1 i loh2 i lol r u1 r u2 r d ports 0, 1, 2, 3, 6, 7, and 8 (excl. p00) v i = 0 v ports 4, 5, and 10 v o = v dd C 2.0 v port 9 v i = v dd v dd = 5.0 v 10 % v dd = 3.0 v 10 % v dd = 5.0 v 10 % v dd = 3.0 v 10 % v dd = 5.0 v 10 % v dd = 3.0 v 10 %
43 m pd75036 notes 1. this current excludes the current which flows through the built-in pull-up resistors. 2. this value applies also when the subsystem clock oscillates. 3. value when the processor clock control register (pcc) is set to 0011 and the m pd75036 is operated in the high-speed mode 4. value when the pcc is set to 0000 and the m pd75036 is operated in the low-speed mode 5. this value applies when the system clock control register (scc) is set to 1001 to stop the main system clock pulse and to start the subsystem clock pulse. ma ma m a m a m a m a m a m a m a 3.2 0.25 500 150 15 5 0.5 0.1 0.1 10 0.75 1500 450 45 15 20 10 5 symbol i dd1 i dd2 i dd3 i dd4 i dd5 conditions power supply current note 1 t a = 25 ?c v dd = 3 v 10 % unit max. typ. min. parameter 4.19 mhz note 2 crystal reso- nance c1 = c2 = 22 pf 32.768 khz note 5 crystal resonance xt1 = 0 v stop mode v dd = 5 v 10 % note 3 v dd = 3 v 10 % note 4 halt mode v dd = 5 v 10 % v dd = 3 v 10 % v dd = 3 v 10 % halt mode v dd = 3 v 10 % v dd = 5 v 10 %
44 m pd75036 ac characteristics (t a = -40 to +85 c, v dd = 2.0 to 6.0 v) notes 1. the cycle time of the cpu clock ( f ) depends on the connected resonator frequency, the system clock control reg- ister (scc), and the processor clock control register (pcc). the figure on the right side shows the cycle time t cy characteristics for the supply voltage v dd during main system clock operation. 2. this value becomes 2t cy or 128/f x ac- cording to the setting of the interrupt mode register (im0). parameter symbol t cy f ti t tih , t til t inth , t intl t rsl cpu clock cycle time (minimum instruction execution time = 1 machine cycle) note 1 ti0 input frequency ti0 input high/low level width interrupt input high/low level width reset low level width min. typ. max. unit 122 64 64 125 1 275 m s m s m s mhz khz m s m s m s m s m s m s 0.95 3.8 114 0 0 0.48 1.8 note 2 10 10 10 v dd = 4.5 to 6.0 v operated by main system clock pulse operated by subsystem clock pulse v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v int0 int1, int2, and int4 kr0 to kr7 conditions 70 64 60 6 5 4 3 2 1 0.5 0123 456 operation guaranteed range t cy vs v dd (main system clock in operation) power supply voltage v dd [v] cycle time t cy [ s] m
45 m pd75036 serial transfer operation two-wire and three-wire serial i/o modes (sck ... internal clock output): two-wire and three-wire serial i/o modes (sck ... external clock input): note r l and c l are the resistance and capacitance of the so output line load respectively. min. 1600 3800 t kcy1 /2 C 50 t kcy1 /2 C 150 150 400 0 0 symbol t kcy1 t kl1 t kh1 t sik1 t ksi1 t kso1 parameter sck cycle time sck high/low level width si setup time (referred to sck ) si hold time (referred to sck ) delay time from sck ? to so output r l = 1 k w, c l = 100 pf note v dd = 4.5 to 6.0 v typ. unit ns ns ns ns ns ns ns ns max. 250 1000 conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v symbol t kcy2 t kl2 t kh2 t sik2 t ksi2 t kso2 parameter sck cycle time sck high/low level width si setup time (referred to sck ) si hold time (referred to sck ) delay time from sck ? to so output min. 800 3200 400 1600 100 400 0 0 typ. max. 300 1000 unit ns ns ns ns ns ns ns ns conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w, c l = 100 pf note v dd = 4.5 to 6.0 v
46 m pd75036 t kcy3 t kl3 t kh3 t sik3 t ksi3 t kso3 t ksb t sbk t sbl t sbh sbi mode (sck ... internal clock output (master)): sbi mode (sck ... external clock input (slave)): note r l and c l are the resistance and capacitance of the sb0/sb1 output line load respectively. 250 1000 1600 3800 t kcy3 /2 - 50 t kcy3 /2 - 150 150 t kcy3 /2 0 0 t kcy3 t kcy3 t kcy3 t kcy3 ns ns ns ns ns ns ns ns ns ns ns ns v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf note conditions parameter min. typ. max. unit sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck ) sb0/sb1 hold time (referred to sck ) delay time from sck ? to sb0/sb1 output from sck to sb0/sb1 ? from sb0/sb1 ? to sck ? sb0/sb1 low level width sb0/sb1 high level width symbol parameter t kcy4 t kl4 t kh4 t sik4 t ksi4 t kso4 t ksb t sbk t sbl t sbh 300 1000 min. unit max. typ. conditions v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v r l = 1 k w , c l = 100 pf note v dd = 4.5 to 6.0 v 800 3200 400 1600 100 t kcy4 /2 0 0 t kcy4 t kcy4 t kcy4 t kcy4 sck cycle time sck high/low level width sb0/sb1 setup time (referred to sck ) sb0/sb1 hold time (referred to sck ) delay time from sck ? to sb0/sb1 output from sck to sb0/sb1 ? from sb0/sb1 ? to sck ? sb0/sb1 low level width sb0/sb1 high level width symbol ns ns ns ns ns ns ns ns ns ns ns ns
47 m pd75036 symbol parameter conditions -10 ta +85?c -40 ta < -10?c min. max. unit typ. t conv t samp v ian av dd av ref+ av ref- r an ai ref 8 av ref- 2.5 2.5 0 8 1.5 2.0 168/f x 44/f x av ref+ v dd av dd 1.0 2.0 2.5 v av ref v dd 2.5 v (av ref +) C (av ref -) 2.5 v (av ref +) C (av ref -) bit lsb m s m s v v v v m w ma 8 1000 1.0 a/d converter (t a = -40 to +85 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v) notes 1. absolute accuracy excluding quantization error ( 1/2 lsb) 2. time from the execution of a conversion start instruction till the end of conversion (eoc = 1) (40.1 m s: f x = 4.19 mhz) 3. time from the execution of a conversion start instruction till the end of sampling (10.5 m s: f x = 4.19 mhz) 4. the value resulting from subtracting (av refC ) from (av ref+ ) must be greater than or equal to 2.5 v. resolution absolute accuracy note 1 conversion time note 2 sampling time note 3 analog input voltage analog power supply voltage reference input voltage note4 reference output voltage note 4 analog input imped- ance av ref current
48 m pd75036 ac timing measurement points (excluding (x1 and xt1 inputs) c lock timing ti0 timing measurement point 0.2v dd 0.8v dd 0.2v dd 0.8v dd t xl t xh 1/f x x1 input v dd ?0.5 v 0.4 v t xtl t xth 1/f xt xt1 input v dd ?0.5 v 0.4 v t til t tih 1/f ti ti0
49 m pd75036 serial transfer timing three-wire serial i/o mode: two-wire serial i/o mode: t kl1 t kcy1 t sik1 t kh1 t ksi1 t kso1 input data output data sck si so t kcy2 t kl2 t kh2 t ksi2 t sik2 t kso2 sck sb0 and sb1
50 m pd75036 serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing sck sb0 and sb1 t ksb t sbl t sbh t sbk t kcy3 t kcy4 t kso3 t kso4 t kl3 t kl4 t kh3 t kh4 t ksi3 t ksi4 t sik3 t sik4 sck sb0 and sb1 t ksb t kl3 t kl4 t kcy3 t kcy4 t kso3 t kso4 t sbk t kh3 t kh4 t sik3 t sik4 t ksi3 t ksi4 int0, int1, int2 and int4 kr0-kr7 t intl t inth reset t rsl
51 m pd75036 parameter symbol data hold supply voltage data hold supply current note 1 release signal setting time oscillation settling time note 2 v dddr i dddr t srel t wait min. typ. max. unit 2.0 0 0.1 2 17 /f x note 3 6.0 10 v m a m s ms ms v dddr = 2.0 v release by reset release by interrupt request conditions data hold characteristics by low supply voltage in data memory stop mode (t a = -40 to +85 c) notes 1. excluding the current which flows through the built-in pull-up resistors 2. cpu operation stop time for preventing unstable operation at the beginning of oscillation 3. this value depends on the settings of the basic interval timer mode register (btm) shown below. data hold timing (stop mode release by reset) data hold timing (standby release signal: stop mode release by interrupt signal) 0 1 0 1 0 1 1 1 btm0 btm1 0 0 1 1 btm2 btm3 2 20 /f x (approx. 250 ms) 2 17 /f x (approx. 31.3 ms) 2 15 /f x (approx. 7.82 ms) 2 13 /f x (approx. 1.95 ms) wait time (values at fx = 4.19 mhz in parentheses) reset v dd v dddr t srel t wait internal reset operation halt mode operation mode stop instruction execution data hold mode stop mode standby release signal (interrupt request) v dd v dddr t srel t wait halt mode operation mode stop instruction execution data hold mode stop mode
52 m pd75036 11. package dimensions a i j g h f d n m c b m r 64 33 32 1 k l note each lead centerline is located within 0.17 mm (0.007 inch) of its true position (t.p.) at maximum material condition. p64c-70-750a,c-1 item millimeters inches a b c d f g h i j k 58.68 max. 1.778 (t.p.) 3.2?.3 0.51 min. 4.31 max. 1.78 max. l m 0.17 0.25 19.05 (t.p.) 5.08 max. 17.0 n 0~15? 0.50?.10 0.9 min. r 2.311 max. 0.070 max. 0.020 0.035 min. 0.126?.012 0.020 min. 0.170 max. 0.200 max. 0.750 (t.p.) 0.669 0.010 0.007 0~15? +0.004 ?.003 0.070 (t.p.) 1) item "k" to center of leads when formed parallel. 2) +0.10 ?.05 +0.004 ?.005 64 pin plastic shrink dip (750 mil)
53 m pd75036 n a m f b 48 49 32 k l 64 pin plastic qfp ( 14) 64 1 17 16 33 d c detail of lead end s q 55? p m i h j g p64gc-80-ab8-3 item millimeters inches a b c d f g h i j k l 17.6 0.4 14.0 0.2 1.0 0.35 0.10 0.15 14.0 0.2 0.693 0.016 0.039 0.039 0.006 0.031 (t.p.) 0.551 note m n 0.10 0.15 1.8 0.2 0.8 (t.p.) 0.004 0.006 +0.004 ?.003 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.071 0.008 0.014 0.551 0.8 0.2 0.031 p 2.55 0.100 0.693 0.016 17.6 0.4 1.0 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 2.85 max. 0.112 max. +0.10 ?.05 +0.009 ?.008 +0.004 ?.005 +0.009 ?.008
54 m pd75036 appendix a development tools the following development tools are provided for developing systems including the m pd75036: notes 1 . maintenance service only 2 . not contained in the ie-75001-r 3 . these software cannot use the task swap function, which is available in ms-dos ver. 5.00 and ver. 5.00a. h in-circuit emulator for the 75x series emulation board for the ie-75000-r and ie-75001-r emulation probe for the m pd75036cw emulation probe for the m pd75036gc. a 64-pin conversion socket, the ev-9200gc-64, is attached to the probe. prom programmer prom programmer adapter for the m pd75p036cw. connected to the pg-1500. prom programmer adapter for the m pd75p036gc. connected to the pg-1500. ie-75000-r note 1 ie-75001-r ie-75000-r-em note 2 ep-75028cw-r ep-75028gc-r pg-1500 pa-75p036cw pa-75p036gc ev-9200gc-64 ie control program pg-1500 controller ra75x relocatable assembler hardware software host machine ? pc-9800 series (ms-dos tm ver. 3.30 to ver. 5.00a note 3 ) ? ibm pc/at tm series (pc dos tm ver. 3.10)
55 m pd75036 appendix b related documents documents related to the device documents related to development tools other documents caution the above documents may be revised without notice. use the latest versions when you design an application system. users manual application note 75x series selection guide document name document no. ieu-1294 iem-1294 if-1027 eeu-1297 eeu-1416 eeu-1294 eeu-1314 eeu-1306 eeu-1335 eeu-1346 eeu-1363 eeu-1291 operation language ie-75000-r users manual ie-75001-r users manual ie-75000-r-em users manual ep-75028cw-r users manual ep-75028gc-r users manual pg-1500 users manual ra75x assembler package users manual pg-1500 controller users manual hardware software document no. document name package manual smd surface mount technology manual quality grades on nec semiconductor devices nec semiconductor device reliability/quality control system electrostatic discharge (esd) test guide to quality assurance for semiconductor devices document no. document name iei-1213 iei-1207 iei-1209 iei-1203 iei-1201 mei-1202 h
56 m pd75036 [memo]
57 m pd75036 cautions on cmos devices 1 countermeasures against static electricity for all moss caution when handling mos devices, take care so that they are not electrostatically charged. strong static electricity may cause dielectric breakdown in gates. when transporting or storing mos devices, use conductive trays, magazine cases, shock absorbers, or metal cases that nec uses for packaging and shipping. be sure to ground mos devices during assembling. do not allow mos devices to stand on plastic plates or do not touch pins. also handle boards on which mos devices are mounted in the same way. 2 cmos-specific handling of unused input pins caution hold cmos devices at a fixed input level. unlike bipolar or nmos devices, if a cmos device is operated with no input, an intermediate- level input may be caused by noise. this allows current to flow in the cmos device, resulting in a malfunction. use a pull-up or pull-down resistor to hold a fixed input level. since unused pins may function as output pins at unexpected times, each unused pin should be separately connected to the v dd or gnd pin through a resistor. if handling of unused pins is documented, follow the instructions in the document. 3 statuses of all mos devices at initialization caution the initial status of a mos device is unpredictable when power is turned on. since characteristics of a mos device are determined by the amount of ions implanted in molecules, the initial status cannot be determined in the manufacture process. nec has no responsibility for the output statuses of pins, input and output settings, and the contents of registers at power on. however, nec assures operation after reset and items for mode setting if they are defined. when you turn on a device having a reset function, be sure to reset the device first.
m pd75036 68 [memo] no p art of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties b y or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for uses in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for the applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard: computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special: automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime system, etc. ms-dos is a trademark of microsoft corporation. pc dos and pc/at are trademarks of ibm corporation. m4 92.6

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